C6000 AET Logic

Advanced Event Triggering (AET) Logic

Overview

Advanced Event Trigger is logic that is included on the CPU core to generate triggers. These triggers can be used for various tasks. They can halt the CPU, increment a counter, turn trace capture on/off, or generate an interrupt among other things. The AET unit consists of counters, address comparators, event signals, and a state machine that can all be configured to generate triggers based on some preset logic.

Warning:

This description is for the C6000 family of cores.

Trigger Builders

Trigger Builders perform the job of implementing the logic table that defines the state relationship between a set of 4 input signals and output trigger. The 64x and 64x+ devices implemented with AET have a total of 14 trigger builders. Each trigger builder is a member of one of three families, the 7-Wide, 3-Wide, and 1-Wide. Of the 14 trigger builders, 2 are 7-Wide and there are 6 each of the 3-Wide and 1-Wide.

Each trigger builder is hard wired to a specific set of events. So, in order to generate a Halt CPU trigger, a Trigger Builder that can generate a Halt CPU trigger must be selected. The user doesn't need to be aware of which trigger builders are connected to which events, as UBM or AETLIB will take care of that for them. However, it's convenient to understand that trigger builders are limited resources and there can potentially be conflicts if multiple jobs need to use the same trigger builder.

Diagram of a 1-Wide Trigger Builder

1-Wide Trigger Builder

A 1-wide trigger builder is used for generating a single trigger. Examples include CPU Halt, Emulation Interrupt, Start/Advance Counter, Trace End, and Trace Marker. In the diagram, you can see the simplified logic of the 1-Wide trigger builder. Notice that there are a single set of four inputs. The lookup table defines the output based on the combinational logic of the inputs. The demultiplexer takes the output of the lookup table and directs it to the specified output trigger.

Diagram of a 3-Wide Trigger Builder

1-Wide Trigger Allocation

Trigger Builder #	Output Control	Trigger Output
1 - Wide TB 0	0	Halt CPU
	1	AINT
	2	Trace Marker
	3	Trace End
1 - Wide TB 1	0	Start/Advance Counter 0
	1	Reserved
	2	HALT CPU
	3	AINT
1 - Wide TB 2	0	Stop/Reload Counter 0
	1	Trace End
	2	Halt CPU
	3	AINT
1 - Wide TB 3	0	Start/Advance Counter 1
	1	Reserved
	2	Halt CPU
	3	AINT
1 - Wide TB 4	0	Stop/Reload Counter 1
	1	Trace End
	2	Halt CPU
	3	AINT
1 - Wide TB 5	0	Trace Marker
	1	Trace End
	2	Reserved
	3	Halt CPU

3-Wide Trigger Builder

A 3-wide trigger builder is used for potentially generating 3 different triggers based on the same set of input events. A 3-wide trigger builder consists of 3 different lookup tables that allow generation of 3 different triggers based on combinations of the same set of event inputs. One example of a potential use for 3-wide trigger builders would be the Suspend Trace triggers (Suspend PC/Suspend Timing/Suspend Data). Another example is transition to one of the states in the state machine.

In the diagram of the 3-wide trigger builder, you can see that the architecture is basically just multiple copies of the single wide trigger builder, with one exception. As you'll notice, the input events and the output control select are shared between all of the trigger builders in that group. This is an important point. If Output 0 is selected on a multiple wide trigger builder, it is selected for all of the triggers. Also, the inputs are the same for each lookup table. The triggers can be generated by different combinations of those 4 events, but the input events are the same for all triggers.

3-Wide Trigger Allocation

Trigger Builder #	Output Control	Trigger Output	Trigger Output 1	Trigger Output 2	Trigger Output 3
3 - Wide TB 0	0	Stop Trace	Stop PC Trace	Stop Timing Trace	Stop Data trace
	1	Suspend Trace	Suspend PC Trace	Suspend Timing Trace	Suspend Data trace
	2	External	External Trigger 0	External Trigger 1	Reserved
	3	Start Watermark	Start Watermark 0	Reserved	Start Watermark 1
3 - Wide TB 1	0	Suspend Trace	Suspend PC Trace	Suspend Timing Trace	Suspend Data trace
	1	Stop Trace	Stop PC Trace	Stop Timing Trace	Stop Data trace
	2	End Watermark	End Watermark 0	End Watermark 1	Reserved
	3	Reserved	Reserved	Reserved	Reserved
3 - Wide TB 2	0	Transition From State 0	State 0-1	State 0-2	State 0-3
	1	Reserved	Reserved	Reserved	Reserved
	2	Reserved	Reserved	Reserved	Reserved
	3	Stop Trace	Stop PC Trace	Stop Timing Trace	Stop Data Trace
3 - Wide TB 3	0	Transition From State 1	State 1-0	State 1-2	State 1-3
	1	Reserved	Reserved	Reserved	Reserved
	2	Reserved	Reserved	Reserved	Reserved
	3	Suspend Trace	Suspend PC Trace	Suspend Timing Trace	Suspend Data Trace
3 - Wide TB 4	0	Transition From State 2	State 2-0	State 2-1	State 2-3
	1	Reserved	Reserved	Reserved	Reserved
	2	Halt CPU	Halt CPU	Reserved	Reserved
	3	Stop Trace	Stop PC Trace	Stop Timing Trace	Stop Data Trace
3 - Wide TB 5	0	Transition From State 3	State 3-0	State 3-1	State 3-2
	1	Reserved	Reserved	Reserved	Reserved
	2	Halt CPU	Halt CPU	Reserved	Reserved
	3	Suspend Trace	Suspend PC Trace	Suspend Timing Trace	Suspend Data Trace

7-Wide Trigger Builder

A 7-wide trigger builder is used for potentially generating 7 different triggers based on the same set of input events. A 7-wide trigger builder consists of 7 different lookup tables that allow generation of 7 different triggers based on combinations of the same set of event inputs. The 7-wide trigger builder is designed to be used for trace capture triggers. There are 7 different types of trace capture (PC/Timing/Read Address/Read Data/Write Address/Write Data/PC Tag), and the 7-wide trigger builder will allow configuration to generate these triggers based on different combinations of inputs.

In order to save space, the 7-Wide trigger builder diagram is not included, but it can be extrapolated from the diagram of the 3-Wide trigger builder. The 7-Wide trigger Builder provides a total of 7 different 16-bit lookup tables that all share the same inputs and Output select.

7-Wide Trigger Allocation

Trigger Builder #	Output Control	Function	Trig. Output 1	Trig. Output 2	Trig. Output 3	Trig. Output 4	Trig. Output 5	Trig. Output 6	Trig. Output 7
7 - Wide TB 0	0	Store Trace	Store Timing	Store PC	Store Read Address	Store Write Address	Store Read Data	Store Write Data	Store PC Tag
	1	External	External Trigger 0	External Trigger 1	Reserved	Reserved	Reserved	Reserved	Reserved
	2	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
	3	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
7 - Wide TB 1	0	Start Trace	Start Timing	Start PC	Start Read Address	Start Write Address	Start Read Data	Start Write Data	Start PC Tag
	1	Store Trace	Reserved	Store Timing	Store Read Address	Store Write Address	Store Read Data	Store Write Data	Store PC Tag
	2	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
	3	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved

Trigger Behavior

• Start/Stop Triggers

The start and stop triggers are level triggers, not edge triggers. A new window is opened in the same cycle that the trigger is high. The window remains open up to and inclusive of the cycle in which the stop trigger is high.

In the case of Start and Stop trace triggers, this means that Trace will capture data on the cycle where the start trigger is generated, and will continue to capture up to and including the cycle where the stop trigger is generated. If another start trigger is generated on the cycle after the stop trigger is generated, the trace output will appear as if the end trigger never occurred (i.e. there will be no gap in the data between the end trigger and the next start trigger)

Corner Case If the window is closed, and the start and stop trigger are both high simultaneously for one cycle, a one cycle window is created. In the case of trace start/stop triggers, one cycle of trace data will be collected.

Trigger Action Descriptions

• Halt CPU - Halts execution of the CPU. CPU Halt can only be asserted if a debugger is connected to the target. If this trigger is generated in a target that is not connected to the debugger, no action is taken.

• AINT - Auxiliary Interrupt - Generates an interrupt to the CPU. This interrupt is sometimes referred to as the Emulation Interrupt, or RTOS interrupt.

• Counters
  • Start/Advance Counter (Depends on mode of the counter)
    • Start/Stop Mode - High level starts the counter on the same cycle. Counter will decrement on each cycle until the Stop/Reload trigger occurs.
    • Counter Mode - For each CPU clock cycle that the trigger is active, the counter will decrement by 1.
  • Stop/reload Counter
    • Start/Stop Mode - High level will stop the counter on the next cycle.
    • Counter Mode - The counter is reloaded with the value that is in the Counter Reload register.

• Watermark Window
  • Start Watermark Window - High level opens the watermark window on the same cycle. The start of the watermark window causes the counter to be reloaded with 0xFFFFFFF. Any activity on this trigger is ignored if the watermark window has already been started.
  • Stop Watermark Window - High level will stop the watermark window on the next cycle. On the closing of the watermark window, the MAX or MIN value is updated.

• State Transitions
  • State 0-x : High level causes the state machine that is currently in State 0 to transition to state x (1,2,3)
  • State 1-x : High level causes the state machine that is currently in State 1 to transition to state x (0,2,3)
  • State 2-x : High level causes the state machine that is currently in State 2 to transition to state x (0,1,3)
  • State 3-x : High level causes the state machine that is currently in State 3 to transition to state x (0,1,2)

Trigger Builder Terms

Trigger Builder Input Terms

Each trigger builder has a set of 4 input terms. These terms are referred by the letters A-D, as shown in the image. The inputs to each of these term values will be discussed in this section.

Terms A & B

Terms A and B have identical logic connected at the input. The logic effectively consists of a 16-input OR gate with individual enables on each of its input signals. The inputs to the OR gate are events routed from the PC/Data Comparators and the Auxilliary Event Generators. These terms are typically used to to generate triggers based on the execution state of the CPU. Examples include triggering when the program counter is within a specific range of values, triggering when a data value is read or written to a specific range of locations, or triggering when a certain event or subset of events occur.

A and B Terms

The duplication of the A and B logic allows triggers to be generated on a more flexible combination of events. It allows the implementation of a boolean product of sums for the inputs to the 16-input OR gates, using the two OR gates to implement the sum term, and the lookup table to implement the product term. Without the duplication, we would only be able to implement a boolean OR of the events.

See the diagram of the A and B term inputs for a clearer idea of the logic view. The signals at the input of the OR gates are listed below.

A/B Terms OR Inputs

Input #	Description
0	PC/Data Comparator 0
1	PC/Data Comparator 1
2	PC/Data Comparator 2
3	PC/Data Comparator 3
4	PC Comparator 4
5	PC Comparator 5
6	Not Implemented
7	Not Implemented
8	Not Implemented
9	Not Implemented
10	Selective AEG 0
11	ORed AEG 1
12	ORed AEG 2
13	ORed AEG 3
14	ORed AEG 4
15	Reserved

Term C

The C Trigger Builder Term handles the AET Counter Zero Signals. There are two AET Counters (CNT_0, CNT_1) that can be configured to count various events. The counters work in a decrementing fashion. When the counter gets to the value 0, the Counter 0 Signal goes high. This allows the trigger builders to implement complex logic, such as halting when a PC is encountered for the Nth time, or storing trace samples every N cycles.

The logic at the input of term C is a multiplexer that allows selection of the CNT_0 or CNT 1 Zero signal.

Term D

The D term of the trigger builder handles the finite state machine state qualification. The Logic at the input of Term D is a multiplexer that can be configured to select between one of the four states. The finite state machine can be used to enable very complicated triggering logic. The lookup table logic can be configured to only generate a trigger when the given state signal is high.

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