Advanced Debug Feature Plugin View

CortexA9 Advanced Feature View

• When the "Establish Data-Side Coherency" button is selected, the following operations are performed:
  •  The entire data cache is cleaned by set/way using a "cp15 c7 0 c10 2"operation on each line in the cache (1)
  • A 'DSB' opcode is executed, with full system shareability domain (which insures that all prior memory ops are completed), then the store buffers are drained (2)
• When the "Establish Instruction-Side Coherency" button is selected, the following operations are performed:
  • The entire instruction cache is invalidated using a "cp15 c7 0 c1 0" operation, which invalidates all instruction caches to PoU (point-of-unification) inner shareable (3)
  • An 'ISB' opcode is executed, which flushes the pipeline and synchronizes the branch-predictor array (4)
• When the "Establish Global IMB" button is selected, the above listed operations are performed in the following order: 1, 2, 3, 4.
• These operations establish coherency at the L1 cache level - no L2operations are performed.

Hints and Tips

• The Cortex A9 driver does not currently set a global IMB after a program download - this means that to properly setup the cortexA9 for execution after a download, the "Establish Global IMB" MUST be executed by the user. Failure to do so will lead to unexpected results, as the instruction cache will likely not contain the correct opcodes