AM437x Power Consumption Summary

CAUTION Data presented in this wiki was collected on an unsupported version of the SDK, and is provided for legacy purposes. For most recent data, please refer to the TI Processor SDK Kernel Performance Guide, Power Management section

Overview

Note: the power consumption data in this Wiki was last collected on February 18, 2014

The AM437x Power Consumption Summary discusses the power consumption for common system application usage scenarios for the AM437x ARM® Cortex™-A8 Microprocessors (MPUs). The metrics contained in this document serve to give users a better understanding of AM437x active power behaviors -- making it easier to determine a suitable configuration to meet a given power budget. Power consumption is highly dependent on the individual user’s application; however, this document focuses on providing several AM437x application-usage case scenarios and the environment settings that were used to perform such power measurements. This collection of real power measurements was measured on AM437x EVMs with a high-precision digital multimeter.

For additional details about the AM437x processor, please visit the TI.com product page.

Power Measurement Setup

The power measurements have been performed on the following platform:

• Texas Instruments AM437x GP EVM 1.2A
  
• Texas Instruments AM437x LPDDR2 EVM 1.2B (The LPDDR2 EVM is for internal development only and not available for purchase.)
  
• Texas Instruments 2Mp Camera Board 1.2A
  
• Keithley 2701 DMM with a 7702 40-channel mux module.
• All tests were not conducted in a controlled environment. The ambient room temperature was ~25C.

AM437x Power Supplies

The following table describes the power supplies for AM437x:

AM437x Power Supply rails

SIGNAL	DESCRIPTION	VALUE
VDD_CORE	Core domain	0.95V - 1.1V
VDD_MPU	MPU domain	0.95V - 1.325V
VDDS_DDR	DDR IO domain (LPDDR2 / DDR3(L))	1.2V / 1.35V / 1.5V
VDDS	Dual voltage IO domains	1.8V
VDDS_SRAM_CORE_BG	Core SRAM LDOs, Analog	1.8V
VDDS_SRAM_MPU_BB	MPU SRAM LDOs, Analog	1.8V
VDDS_PLL_DDR	DPLL DDR, Analog	1.8V
VDDS_PLL_CORE_LCD	DPLL Core and LCD, Analog	1.8V
VDDS_PLL_MPU	DPLL MPU, Analog	1.8V
VDDS_OSC	System oscillator IOs, Analog	1.8V
VDDA_ADC0/1	ADC, Analog	1.8V
VDDS_CLKOUT	CLKOUT voltage domain	1.8V
VDDA1P8V_USB0/1	USB PHY, Analog, 1.8V	1.8V
VDDA3P3V_USB0/1	USB PHY, Analog, 3.3V	3.3V
VDDSHV1/2/3/5/6/7/8/9/10/11	Dual Voltage IO domain	1.8/3.3V
CAP_VDD_RTC	RTC domain	1.1V
VDDS_RTC	RTC domain	1.8V

The "DDR3" measurements have an additional "VDDS_DDR" supply, which is brought up on the Rev1.2A GP EVM. This is not an AM437x voltage rail. It is used to measure the power consumption of four DDR3 devices + VTT.

High-level Summary

The following tables contain a high-level summary of the total device power (measured in milliwatts) for each application use case and/or configuration.

Low Power Modes

"Max" accounts for additional leakage power due to worst-case silicon process variation, at room temperature.

• "Typical" refers to nominal silicon, at room temperature
• "Max" accounts for additional leakage power due to worst-case silicon process variation, at room temperature

	Typical (mW)	Max (mW)
DeepSleep	4.00	4.50

Active Modes

Selected demo applications from the AM437x Linux SDK.

• VDD_CORE and VDD_MPU at OPP100 (ARM 600 MHz, L3 200 MHz, L4 100 MHz)
• "DDR3" refers to AM437x Rev. 1.2A GP EVM, which has four DDR3 devices with VTT termination at running 400 MHz
• "LPDDR2" refers to AM437x Rev. 1.2B LPDDR2 EVM, which has dual-loaded LPDDR2 running at 266 MHz. The LPDDR2 EVM is for internal development only and not available for purchase.

• GP EVM Clock Configuration: ARM 600 MHz, DDR3 400 MHz, L3 200 MHz, L4 100 MHz, PER 192 MHz, DISP 48 MHz
• LPDDR2 EVM Clock Configuration: ARM 600 MHz, LPDDR2 266 MHz, L3 200 MHz, L4 100 MHz, PER 192 MHz, DISP 48 MHz

Application	DDR3+VTT (mW)	LPDDR2 (mW)
OS Idle w Matrix Qt GUI	698	495
Dhrystone	915	703
Whetstone	888	653
DDR Bandwidth	844	625
AAC Decode	734	489
H.264 Decode	971	664
3D Chameleon Man	1059	695
Camera	930	566

MPU DVFS

Dynamic Voltage Frequency Scaling (DVFS) for the MPU voltage domain. VDD_CORE is maintained at OPP100.

Total SoC Power

		DDR3+VTT		LPDDR2
MPU OPP	MPU Freq (MHz)	Linux Idle (mW)	Dhrystone (mW)	Linux Idle (mW)	Dhrystone (mW)
OPP50	300	504	597	336	419
OPP100	600	557	785	385	607
OPP120	720	588	924	422	742
Turbo	800	621	1033	446	833
Nitro	1000	671	1252	504	1038

VDD_MPU Power

		DDR3+VTT		LPDDR2
MPU OPP	MPU Freq (MHz)	Linux Idle (mW)	Dhrystone (mW)	Linux Idle (mW)	Dhrystone (mW)
OPP50	300	31	118	29	110
OPP100	600	82	313	76	294
OPP120	720	117	449	109	423
Turbo	800	143	550	134	516
Nitro	1000	201	766	188	714

MPU DFS

Dynamic Frequency Scaling (DFS) for the MPU clock. VDD_MPU is maintained at 1.1 V. VDD_CORE is maintained at OPP100.

VDD_MPU Power

		DDR3+VTT		LPDDR2
MPU_MPU (V)	MPU Freq (MHz)	Linux Idle (mW)	Dhrystone (mW)	Linux Idle (mW)	Dhrystone (mW)
1.1	50	10	30	10	28
1.1	100	17	57	16	53
1.1	200	31	110	28	102
1.1	300	43	163	40	151
1.1	400	56	215	52	199
1.1	500	69	266	64	247
1.1	600	82	317	76	294

CORE OPP

CORE OPP for the VDD_CORE voltage domain.

• Total SoC and VDD_CORE power were measured with different CORE OPP, DDR Frequency and DDR configurations.
• CORE OPP cannot be dynamically changed

With LPDDR2

Total SoC Power

CORE OPP	No-OS Idle (mW)	LCD Test (mW)	Camera Test (mW)
OPP50	180	230	304
OPP100	288	375	472

VDD_CORE Power

CORE OPP	No-OS Idle (mW)	LCD Test (mW)	Camera Test (mW)
OPP50	74	94	97
OPP100	174	225	233

With DDR3+VTT

Total SoC Power

CORE OPP	No-OS Idle (mW)	LCD Test (mW)	Camera Test (mW)
OPP100	570	686	767

VDD_CORE Power

CORE OPP	No-OS Idle (mW)	LCD Test (mW)	Camera Test (mW)
OPP100	277	342	351