AM37x to AM437x Hardware Migration Guide

Content is no longer maintained and is being kept for reference only!

Introduction

This article documents the differences between the TI AM37x processor and the TI AM437x processor. All of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.

The device folders are found at the following web pages:

• AM37x
• AM437x

Software Migration Guide

For more information on software migration, please see:

TBD

Basic Feature comparison

The figures and table below show a comparison of the basic features of the AM37x and the AM437x. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.

AM37x AM437x block diagram.png

  

Device Family	AM37x	AM437x
Device Family	AM3703 - CortexA8  AM3715 - CortexA8 with SGX 530	AM4376/7 - CortexA9  AM4378/9 - CortexA9 with SGX 530
Package Options
Packages	515-pin s-PBGA (CBP), .5-mm Ball Pitch (top), .4-mm Ball Pitch(bottom) 515-pin s-PBGA (CBC), .65-mm Ball Pitch (top), .5-mm Ball Pitch (bottom) 423-pin s-PBGA (CUS), .65-mm Ball Pitch, layout using .80-mm rules	491-pin BGA, .65-mm Ball Pitch with VCA
Co-processors and Subsystems
ARM Processor	Cortex-A8 up to 1GHz; 32K-Byte Instruction and Data Caches; 256K-Byte L2 Cache	Cortex-A9 up to 1GHz; 32K-Byte Instruction and Data Caches; 256K-Byte L2 Cache
	Supported OPP: 50/100/130/1G	Supported OPP: 50%/100%/120%/Turbo/Nitro
Neon Co-processor	Y	Y
Graphics Engine	SGX530 3D, 200 MHz	SGX530 3D, 200 MHz
System DMA	sDMA	eDMA
PRU-ICSS	N	2
Memory Interfaces:
mDDR/DDR2/DDR3 Controller	SDRC; 16, 32-bit memory controller with 1G-Byte total address space	Single 32-bit LPDDR2/DDR3L/DDR3 SDRAM Supports up to LPDDR2-533, DDR3-800, DDR3L-800 Total 2 GB Total Address Space
GPMC	Y	Y
ELM	Y	Y
On Chip Memory (OCMC)	64KB (general purpose)	256KB (general purpose)
Security
Crypto hardware accelerators	Y	Y
Video Interfaces:
Camera ISP / VPFE	Y	Y
Display	Display SubSystem (DSS)	Display Subsystem (DSS)
Peripherals
USB	1 USB OTG 3 USB Host	Two (2) USB 2.0 High Speed ports with integrated PHY
eMAC	not present	2 (10/100/1000 Mbps)
CAN	not present	2
McASP	not present	2
McBSP	5	not present
UART	4 (1 with IrDA)	6 (all with IrDA)
McSPI	4	5
QSPI	not present	1
I2C	3	3
GPIO	6 banks	6 banks
eCAP	not present	3
eHRPWM	not present	6
eQPE	not present	3
ADC	not present	2 (1 TSC/ADC and 1 ADC)
Removable Media
MMC/SD/SDIO	3	3
D1W/HDQ	Y	Y
Power, Reset, and Clock Management
RTC	not present	Y
Test Interfaces
JTAG	Y	Y
ETM, ETB, & PTM	ETM, ETB	PTM
IEEE support	IEEE 1149.1	IEEE 1500
Misc
GP Timer	11	12
Watchdog Timer	2	1
32-kHz Sync Timer	1	1

Module Comparison

Processors

ARM Core

AM37x is based on the ARM Cortex-A8 processor. AM437x is based on the ARM Cortex-A9 processor. The table below shows a comparison between these two devices.

AM37x and AM437x ARM Processor Comparison

ARM Processor	AM37x	AM437x
ARM Processor	ARM Cortex™ A8	ARM Cortex™ A9
Revision	r3p2	r2p10
Operating Performance Points	OPP50, OPP100, OPP130, OPP1G*	OPP50, OPP100, OPP120, Turbo, Nitro
Operating Voltages	.97V, 1.14V, 1.27V, 1.33V*	.95V, 1.1V, 1.2V, 1.26V, 1.325V
Operating Frequencies	300MHz, 600MHz, 800MHz, 1000MHz	300MHz, 600MHz, 720MHz, 800MHZ, 1000MHz
L1 Instruction Cache	32 Kbytes	32 Kbytes
L1 Data Cache	32 Kbytes	32 Kbytes
L1 with PED	No	Yes
L2 Cache	256 Kbytes	256 Kbyte
L2 with ECC	No	No
ROM Size	96 Kbytes (64 KB Secure ROM and 32 KB of Boot ROM)	64 Kbytes
RAM Size	64 Kbytes (62Kbytes Secure RAM and 2Kbytes Public RAM)	64 Kbytes

                                                           * OPP 1G available with SmartReflex enabled.

                                                            Note: Please refer to the AM37x and AM437x Datasheets for the latest OPP values.

Neon Co-processor

The Neon co-processor is the same between the two devices.

Wake-up Controller

AM437x has a Wake-up controller that manages entry and exit of various stand-by and deep-sleep modes.

AM37x does not contain a dedicated wake-up controller.

Graphics Engine

The SGX530 3D Graphics Engine is the same between both devices.

On-Chip Memory

AM37x has 64KB of general purpose on-chip memory controller (OCMC) RAM.

AM437x has 256KB of general purpose on-chip memory controller (OCMC) RAM.

Memory Subsystem

General Purpose Memory Controller

AM37x supports 8 chip selects.

AM437x supports 7 chip selects.

The GPMC module is binary compatible between the two devices. The only differences are the ECC hardware mechanism, which is outside of the GPMC module and that AM437x supports 26 address lines for memory mapped devices such as NOR flash, and AM37x supports 12 address lines.

ECC

AM37x supports 1-bit (Hamming) and 4-bit, 8-bit (BCH) hardware ECC. AM37x ROM supports 1-bit ECC.
AM437x supports 1-bit (Hamming) ECC and has a new Error Locator Module (ELM) to support 4-bit, 8-bit, or 16-bit (BCH) ECC.

External Memory Interface

AM37x supports the SDRC Subsystem, providing a 16- or 32-bit interface up to 1 GB (total) to LPDDR.

• 32-bit LPDDR 200-MHz Clock (LPDDR-400 Data Rate)

The SDRC Sybsystem includes a SDRAM memory scheduler (SMS) and a virtual rotated frame-buffer (VRFB) within the subsystem supports rotations of 0/90/180/270 degrees.

AM437x supports a single 32-bit LPDDR2(discrete or non-POP)/DDR3L/DDR3 SDRAM Interface, with up to:

• LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
• DDR3: 400-MHz Clock ( DDR3-800 Data Rate)
• DDR3L: 400-MHz Clock (DDR3L-800 Data Rate)

One x32 device, two x16 devices, or four 8x devices and 2 GB (total) of address space are supported. The EMIF does not support Virtual Rotated Frame Buffer (VRFB) 0/90/180/270 degree rotation in hardware.

Power, Reset, and Clock Management

Operating Performance Points

AM37x Operating Performance Points

OPP	ARM Frequency (MHz)	Voltage (V)
OPP1G *	1000	1.33
OPP130	800	1.27
OPP100	600	1.14
OPP50	300	0.97

* OPP 1G available with SmartReflex enabled.

Note: Please refer to the AM37x Datasheet for the latest OPP values.

AM437x Operating Performance Points

OPP	ARM Frequency (MHz)	Voltage (V)
Nitro	1000	TBD
Turbo	800	TBD
OPP130	720	TBD
OPP100	600	TBD
OPP50	300	TBD

Note: Please refer to the AM437x Datasheet for the latest OPP values.

 Voltage Rails 

The following table compares the power supplies for AM37x and AM437x:

AM37x Voltage Rails

SIGNAL	DESCRIPTION	VALUE
vdd_mpu_iva	MPU	0.97V - 1.33V *
vdd_core	Core	0.97V - 1.33V *
vdds	1.8-V I/O	1.8V
vdds_mem	Memory buffers	1.8V
vdds_mmc1	MMC1 dual voltage I/Os	1.8V / 3.0V
vdds_x	x dual voltage I/Os	1.8V / 3.0V
vdda_wkup_bg_bb	Wake-up LDO	1.8V
vdda_dac	Video DAC	1.8V
vdds_sram	SRAM LDOs	1.8V
vdda_dplls_dll	MPU, core DPLLs and DLL	1.8V
vdda_dpll_per	DPLLs (peripherals)	1.8V
vssa_dac	Ground for video buffers and DAC	0V
vss	Main ground	0V

*  Note: Please refer to the AM37x Datasheet for the latest values.

AM437x Voltage Rails

SIGNAL	DESCRIPTION	VALUE
VDD_CORE	Core domain	TBD *
VDD_MPU	MPU domain	TBD *
CAP_VDD_RTC	RTC domain input/LDO output	1.1V
VDDS_RTC	RTC domain	1.8V
VDDS_DDR	DDR IO domain (DDR2 / DDR3)	1.2V - 1.5V
VDDS	Dual voltage IO domains	1.8V
VDDS_SRAM_CORE_BG	Core SRAM LDOs, Analog	1.8V
VDDS_SRAM_MPU_BB	MPU SRAM LDOs, Analog	1.8V
VDDS_PLL_DDR	DPLL DDR, Analog	1.8V
VDDS_PLL_CORE_LCD	DPLL Core and LCD, Analog	1.8V
VDDS_PLL_MPU	DPLL MPU, Analog	1.8V
VDDS_OSC	System oscillator IOs, Analog	1.8V
VDDA1P8V_USB0	USB PHY, Analog, 1.8V	1.8V
VDDA1P8V_USB1	USB PHY, Analog, 1.8V	1.8V
VDDA3P3V_USB0	USB PHY, Analog, 3.3V	3.3V
VDDA3P3V_USB1	USB PHY, Analog, 3.3V	3.3V
VDDA_ADC0	ADC0, Analog	1.8V
VDDA_ADC1	ADC1	1.8V
VDDSHV1	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV2	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV3	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV4	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV5	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV6	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV7	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV8	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV9	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV10	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
VDDSHV11	Dual Voltage IO domain (1.8V/3.3V operation)	1.8V/3.3V
DDR_VREF	DDR SSTL/HSTL reference input (DDR2/DDR3)	0.50*VDDS_DDR
USB0_VBUS	USB VBUS comparator input
USB1_VBUS	USB VBUS comparator input
USB0_ID	USB ID input	1.8V
USB1_ID	USB ID input	1.8V

* Note: Please refer to the AM437x Datasheet for the latest values.

Input Clocks

AM37x Input Clocks

CLOCK NAME	SOURCE	VALUE
sys_xtalin/out	High Frequency Input Clock	12, 13, 16.8, 19.2, 26, 38.4 MHz
sys_altclk	Alternative Input Clock	48 MHz or 54 MHz
sys_32K	Low Frequency Input Clock	32 KHz

AM437x Input Clocks

CLOCK NAME	SOURCE	VALUE
CLK_M_OSC	Master Oscillator	19.2,  24, 25, 26 MHz
CLK_32KHZ	Divide down of PER PLL output (PLL uses Master Osc)	32768 Hz Precise
CLK_RC_32KHZ	Internal RC Oscillator	16 - 60 kHz
CLK_32K_RTC	External 32768 Hz crystal with internal 32K Osc or external 32768 Hz clock	32768 Hz Precise
CLK_32K_MOSC	Divide down of Master Oscillator Crystal Frequency	Precise 32768 Hz only when using 26MHz crystal

PLLs 

AM37x has the following PLLs, all driven by the HF clock:

• DPLL1 - MPU
• DPLL3 - Core

• DPLL4 - Peripherals

• DPLL5 - Peripherals 2

AM437x has the following PLLs, driven by a crystal (CLK_M_OSC):

• Core PLL - for SGX, L3S, L3F, L4F, L4F_PER, PRU_ICSS_IEP, Debugss, GEMAC, PRU_ICSS OCP 
• Peripheral (Per) PLL - for PRU_ICSS_UART, MMC/SD, SPI, UART, I2C 
• MPU PLL - for MPU Subsystem (includes Cortex A-9)
• Display PLL - for LCD Pixel Clock
• DDR PLL - for EMIF

Power Management Feature Comparison

HW Provisions for Power Optimization/ Control	AM37x	AM437x
Individually Switchable Power Domains	No support for individually ON/OFF of Power Domains	Full support for Individual Power Domain ON/OFF: VDD_MPU, VDD_CORE, VDD_PER, VDD_SGX and SRAMs.
Dynamically gating OFF of Clocks to one/more of groups of modules (clock domains) when inactive to conserve power	Supported	Supported
Operating Voltage-Frequencies (OPPs)	OPP50, OPP100, OPP130, OPP1G	OPP50 (VDD_CORE, VDD_MPU), OPP100 (VDD_CORE, VDD_MPU),  OPP120 (VDD_MPU), Turbo (VDD_MPU),  Nitro (VDD_MPU)
Adaptive Voltage Scaling	Class 3 Smart Reflex, VDD1_MPU and VDD2_CORE	Not Supported
SRAM memory retention	Supported	Supported on all memories
HW Auto Clock/Power Domain Dependency Management	Supported	Not Supported
Low Power Deep-Sleep State w/ Auto Wakeup	Not Supported	GPIO0, Timers, USB resume, RTC, UART, TSC, Not supporting wakeup from any IO
RTC Only Cold State	Not Applicable	Supported
Splitting Of Primary Voltage Supply Rails	vdd_mpu_iva, vdd_core	VDD_CORE, VDD_MPU

 

Bootmodes 

Available Bootmodes on AM37x and AM437x

AM37x	AM437x	Boot Type	Description
Y	Y	NOR	This mode allows booting from XIP booting devices, such as NOR flash memories. For AM37x, NOR Flash (up to 2 Gb, or 256M bytes) should be connected to the GPMC peripheral on GPMC_nCS0. GPMC_nCS0 is mapped to address 0x0800_0000. A data bus width of x16 is supported. The GPMC is clocked at 48MHz. For AM437x, NOR Flash (up to 1 Gb, or 128M bytes) should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x16 supported(x8 not supported). The GPMC is clocked at 50MHz. Wait monitoring is also supported and enabled/disabled based on SYSBOOT pins.
Y	Y	NAND	This mode starts downloading code from an NAND memory. For AM37x, NAND flash (from 512Mbit, or 64Mbyte) from should be connected to the GPMC peripheral on GPMC_nCS0. GPMC_nCS0 is mapped to address 0x0800_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 48MHz. For AM437x, NAND flash (from 512Mbit, or 64Mbytes)should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x16 or x8 is supported. The GPMC is clocked at 50MHz.
N	Y	SPI	This mode starts downloading code from an SPI EEPROM or SPI Flash. For AM437x, the SPI device should be connected to the SPI0 peripheral on CS0.
N	Y	QSPI	This mode starts downloading code from Quad SPI Flash. For AM437x, the QSPI device should be connected to the QSPI peripheral on CS0.
Y	Y	UART	In this mode, the UART sends a BOOTME request to the UART peripheral and waits for a response along with code from a host processor. AM37x must be booted using a baud rate of 115200. Both devices can only boot from UART3. For AM437x, must be booted using a baud rate of 115200, 8-bit, no parity, 1 stop bit and noflow control. Both devices can only boot from UART0.
Y	Y	MMCSD	This mode starts booting code from an MMC/SD Controller. For AM37x, the MMC/SD cards should connected to either MMC1 or MMC2. 1.8V or 3.3V I/O voltage is supported on MMC1, and only 1.8V I/O voltage is supported on MMCC2. (External transceiver mode on MMC2 is not supported.) The supported clock frequencies are up to 400 kHz (identification mode) and 20 MHz (data transfer mode). For AM437x, an MMC/SD card or eMMC/eSD/managed NAND memory device can connect to MMC0 or MMC1 interface. Support for 3.3 V or 1.8 V I/O voltages.
N	Y	EMAC	This mode starts booting code from the EMAC port. For AM437x, EMAC boot uses the CPGMAC port 1 of the device.
Y	Y	USB	This mode starts booting code from the USB device. For AM37x, USB boot uses the High Speed or Full Speed USB OTG (USBOTGHS) IP through USB0 interface. For AM437x, two USB boot modes are supported: USB Client Mode operating as a Full-Speed peripheral through the USB0 interface. USB Host Mode operating as a Host supporting boot from SuperSpeed*, High-Speed and Full-Speed mass storage devices through the USB1 interface. Note that USB boot is not supported with AM437x PG1.1. * SuperSpeed devices will enumerate and function as High-Speed devices.

Multimedia Hardware Components

Display

AM437x has a similar Display Subsystem (DSS) to AM37x.

Camera SubSystem

The AM37x contains a camera image signal processor (ISP2P).

The AM437x contains two instantiations of the Video Port Front End (VPFE) camera subsystem.

Communication Interfaces

MMC/SD 

The MMC/SD modules are binary compatible between the two devices. Except, the CLK32 debounce clock is created by dividing the 96-MHz (48-MHz in AM437x) clock in the PRCM by two and then dividing the resulting 48-MHz (24-MHz in AM437x) clock by a fixed 732.4219 in the Control Module to get a 32-kHz clock.

Feature Comparison

FEATURE	AM37x	AM437x
Spec Compliance	MMC v4.2 * SDIO v2.0 SD card v2.0	MMC v4.3 SDIO v2.0 SD card v2.0
Data Width **	8-bit (MMC2/3) 4-bit (MMC1)	8-bit (MMC0/1/2)
Max Clock Rate	48MHz (MCC), 48MHz (SD), 48MHz (SD)	48MHz (MCC), 48MHz (SD), 48MHz (SD)

*  Note full compliance with the MMC command/response sets and MMC bus testing procedure, as defined in the Multimedia Card System Specification, v4.2, does not prevent the use of e.MMC version 4.3 (or 4.4) devices with the AM37x, because e.MMC devices are backward compatible.

**  Note the supported data width is subject to pinmux constraints.

USB

The USB module is different between AM37x and AM437x.

The AM37x requires an external PHY with both the USB-OTG and USB1-3 host ports. Also, the USB1-3 ports are only capable of host mode operation, at either high speed or full speed mode (not both). 

The AM437x contains two USB 2.0 dual-role-device (DRD) subsystems, either of which can be configured as an xHCI Host (HS, FS, LS supported) or as a Device (HS and FS supported).

I2C

The I2C ports are binary compatible between the two devices.

AM37x supports 3 general I2C ports. The I2C ports can support up to 3.4Mbps high speed transmissions, along with the usual 100/400Kbps operation.

AM437x supports 3 general I2C ports. The ports only support 100/400Kbps operation. No high speed mode is supported.

UART

On both Am37x and AM437x, the maximum supported baud rate is 3.6864 Mbps.

AM37x has 4 UARTs. Only UART3 has IrDA capabilities. UART 4 does not support flow control. UART1 and UART2 source CORE_L4_ICLK for the interface clock while UART3 and UART4 use PER_L4_ICLK.

On AM437x, there are 6 UARTs, only UART1 supports full modem control. For UART0 the UART interface clock (CLK) is sourced from M_OSC_CLK in AM437x (max 26MHz), UART 1-5 use the CORE_CLKOUTM4 / 2 at 100MHz.

McBSP/McASP

AM37x has 5 McBSP ports and no McASP ports.

Both AM437x has two McASP ports and no McBSP ports. McASP0/1 support up to 4 McASP serializers.

McSPI

AM37x includes 4 McSPI ports, SPI1 supports up to 4 peripherals and 8 DMA requests to the sDMA, SPI2 and SPI3 support up to 2 peripherals and 8 DMA requests to the sDMA, and SPI4 supports 1 peripheral and 2 DMA requests to the sDMA.

AM437x includes 5 McSPI ports. McSPI[0-2] support 4 chip select signals and 8 DMA requests to the eDMA. McSPI[3-4] only support 2 CS signals and 4 DMA requests to the eDMA.

Timers

GPTimer

AM37x has 11 32-bit GPTimers. Three GPTimers (GPTIMER1, GPTIMER2, and GPTIMER10) support 1-ms tick with 32,768 Hz functional clock generated. Only 4 GPTimers (GPT_8 - GPT_11) are pinned out.

AM437x has 12 General Purpose Timers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 6 GPTimers (DMTIMER0, DMTIMER1, DMTIMER4 - DMTIMER7) are extended to SoC pins. AM437x also adds support for timer cascading, providing a 64-bit timer option. With this feature, DMTIMER2-3 provide a 64-bit internal timer and DMTIMER4-5 provide a 64-bit timer with output capability.

WDTimer 

AM37x has 2 32-bit Watchdog Timers, the MPU WDT which uses the WKUP_L4_ICLK at t32 kHz, and the IVA2 WDT which uses the PER_L4_ICLK 32 kHz clock.

AM437x has one watchdog timer and uses the CLK_M_OSC, providing a max frequency of 26 MHz.

Misc

GPIOs

AM37x supports 6 banks of GPIO signals. Each bank supports 32 GPIOs and two interrupts. All GPIOs are 1.8V I/Os, with the exception of those muxed with MMC1 which are 3.0V capable.

AM437x has 6 banks of GPIOs, each with 32 dedicated IO pins. With the 6 GPIO modules, AM437x allows for a maximum of 192 GPIO pins. Supports a single DMA request for each GPIO module.

INTC

AM335x and AM437x implement different interrupt controllers. Additionally, the interrupt controller on AM37x has 96 interrupt lines. AM437x has 224 interrupt lines.

New interfaces in AM437x

The following are new interfaces in the AM437x device that do not exist in AM37x. Any details about these interfaces can be found in the Technical Reference Manual for AM437x.

• Camera (VPFE)
• PRU-ICSS (Programmable Real-Time Unit SubSystem and Industrial Communication Subsystem)
• Quad-SPI (QSPI)
• EMAC
• CAN
• McASP
• eCAP
• eHRPWM
• eQPE
• TS/ADC
• RTC

Pin and package 

The AM37x and the AM437x devices are offered different mechanical packages. The physical dimensions and pin out of the packages are also different. The table below lists the variations between the AM337x and the AM437x devices.

Pin and Package Comparison

Device	Size (mm)	Pitch (mm)	No. of Pins	POP	Package Designator
AM37x	12 x 12 mm	0.5 mm top, 0.4 mm bottom	515	Supported	s-PBGA (CBP Suffix)
	14 x 14 mm	0.65 mm top, 0.5 mm bottom	515	Supported	s-PBGA (CBC Suffix)
	16 x 16 mm	0.65 mm	423	Not supported	s-PBGA (CUS Suffix)
AM437x	17 x 17 mm	0.65 mm, with VCA	491	Not Supported	BGA (ZDN Suffix)