AM37x To AM335x Hardware Migration Guide

Content is no longer maintained and is being kept for reference only!

Introduction

This article documents the differences between the TI AM37x and the TI AM335x processors. Note that AM37x is the ARM-only version of DM3730 processor. All of the documentation referenced in this migration guide can be found on the TI website located in the two device respective product folders. The device folders are found at the following web pages.

The device folders are found at the following web pages:

• AM37x
• AM335x

Software Migration Guide

For more information on software migration, please see:

TBD

Basic Feature comparison

The table below shows a comparison of the basic features of the AM37x and the AM335x. The remainder of this document presents a comparison of these features in greater detail, and also provides references to the appropriate documentation for further information.

AM37x and AM335x processors

Device Family	AM37x	AM335x
Device Family	AM3703 - CortexA8 AM3715 - CortexA8 with SGX 530	AM3357/6/2 - CortexA8  AM3359/8/4 - CortexA8 with SGX 530
Package Options
Packages	515-pin s-PBGA (CBP), .5-mm Ball Pitch (top), .4-mm Ball Pitch(bottom) 515-pin s-PBGA (CBC), .65-mm Ball Pitch (top), .5-mm Ball Pitch (bottom) 423-pin s-PBGA (CUS), .65-mm Ball Pitch, layout using .80-mm rules	284-pin nFBGA (ZCE), .65-mm Ball Pitch with VCA 324-Pin nFBGA (ZCZ), .80-mm Ball Pitch Full Array
Co-processors and Subsystems
ARM Processor	Cortex-A8 up to 1GHz; 32K-Byte Instruction and Data Caches; 256K-Byte L2 Cache	Cortex-A8 up to 720MHz; 32K-Byte Instruction and Data Caches; 256K-Byte L2 Cache w/ECC
	Supported OPP: 50/100/130/1G	Supported OPP: 50/100/120/SRTurbo
	Trustzone: Supported	Trustzone: Not supported
Neon Co-processor	Y	Y
SGX530 3D Graphics Engine	Y	Y
System DMA	sDMA	eDMA
PRUSS	N	Y
Memory Interfaces:
SDRAM Controller	SDRC; 16, 32-bit memory controller with 1G-Byte total address space	EMIF; 16-bit memory controller with 1G-Byte total address space
General Purpose Memory Controller (GPMC)	1 GB total address space	1 GB total address space
POP	CBP & CBC Package	N
Discrete memory Interface (non PoP)	CUS Package only	ZCE; ZCZ Package
Security
Crypto hardware accelerators	Y	Y
Video Interfaces:
Camera ISP	Y	N
Display	Display SubSystem (DSS)	LCD Controller
Peripherals
USB OTG	1	2
USB Host	3	not present
eMAC	not present	10/100/1000 Mbps
CAN	not present	2
McASP	not present	2
McBSP	5	not present
UART	4 (1 with IrDA)	6 (6 with IrDA)
McSPI	4	2
I2C	3	3
GPIO	6 banks	4 banks
eCAP	not present	3
eHRPWM	not present	3
eQPE	not present	3
ADC/TS	not present	8ch 12bit
HDQ/1-Wire	Y	not present
Removable Media
MMC/SD/SDIO	3	3
Power, Reset, and Clock Management
RTC	not present	Y
Test Interfaces
JTAG	Y	Y
ETM & ETB	Y	Y
IEEE support	IEEE 1149.1	IEEE 1500
Misc
GP Timer	11	7
Watchdog Timer	2	1
32-kHz Sync Timer	1	not present

Module Comparison

Processors

ARM Processor

AM37x and AM335x are both based on the ARM Cortex-A8 processor. The table below shows a comparison between these two devices.

AM37x and AM335x ARM Processor Comparison

ARM Processor	AM37x	AM335x
ARM Processor	ARM Cortex™ A8	ARM Cortex™ A8
Revision	r3p2	r3p2
Operating Performance Points	OPP50, OPP100, OPP130, OPP1G*	OPP50, OPP100, OPP120, SRTurbo
Operating Voltages	.97V, 1.14V, 1.27V, 1.33V*	.95V, 1.1V, 1.2V, 1.26V
Operating Frequencies	300MHz, 600MHz, 800MHz, 1000MHz	275MHz, 500MHz, 600MHz, 720MHz
Trustzone	Supported	Not supported
L1 Instruction Cache	32 Kbytes	32 Kbytes
L1 Data Cache	32 Kbytes	32 Kbytes
L1 with SED	No	Yes
L2 Cache	256 Kbytes	256 Kbytes
L2 with ECC	No	Yes
ROM Size	96 Kbytes (64 KB Secure ROM and 32 KB of Boot ROM)	176 Kbytes (128 KB Secure ROM and 48 KB of Public ROM)
RAM Size	64 Kbytes (62Kbytes Secure RAM and 2Kbytes Public RAM)	64 Kbytes (Secure/ Public RAM)

* OPP 1G available with SmartReflex enabled.
Note: Please refer to the AM37x and AM335x Datasheets for the latest OPP values.

Neon Co-processor

The Neon Coprocessor is the same between the two devices.

Wake-up Controller

AM335x integrates an ARM Cortex M3 core that manages entry and exit of various stand-by and deep-sleep modes.

AM37x does not contain a dedicated wake-up controller.

Graphics Engine

The Graphics Engine SGX530 is binary compatible between the two devices.

On-Chip Memory

AM37x has 64KB RAM.

AM335x has 64KB RAM

External Memory Interfaces

General Purpose Memory Controller

The GPMC module is binary compatible between the two devices. The only difference is the ECC hardware mechanism, which is outside of the GPMC module.

ECC

AM37x supports 1-bit (Hamming) and 4-bit, 8-bit (BCH) hardware ECC.
AM335x supports 1-bit (Hamming) ECC and has a new Error Locator Module (ELM) to support 4-bit, 8-bit, or 16-bit (BCH) ECC.

SDRAM Memory Controller

The SDRAM Memory Controller is different between the two devices.

AM37x supports the SDRC Subsystem, providing a 16- or 32-bit interface to m-SDR and LPDDR. 32-bit LPDDR is only supported up to 200MHz clock frequency. The SDRC Sybsystem includes a SDRAM memory scheduler (SMS) and a virtual rotated frame-buffer (VRFB) within the subsystem supports rotations of 0/90/180/270 degrees.

AM335x supports the EMIF, providing a 16-bit interface to mDDR (LPDDR1), DDR2, and DDR3 memories. The EMIF does not support Virtual Rotated Frame Buffer (VRFB) 0/90/180/270 degree rotation in hardware. The AM335x EMIF supports:

• mDDR: up to 200 MHz clock (400 MHz data rate),
• DDR2: up to 266 MHz clock (532 MHz data rate),
• DDR3: up to 303 MHz clock (606 MHz data rate)

Power, Reset, and Clock Management

Operating Performance Points

AM37x VDD1 Operating Performance Points

OPP	ARM Frequency (MHz)	Voltage (V)
OPP1G *	1000	1.33
OPP130	800	1.27
OPP100	600	1.14
OPP50	300	0.97

* OPP 1G available with SmartReflex enabled.
Note: Please refer to the AM37x Datasheet for the latest OPP values.

AM335x Operating Performance Points

OPP	ARM Frequency (MHz)	Voltage (V)
SRTurbo	720	1.26
OPP120	600	1.20
OPP100	500	1.10
OPP50	275	0.95

Note: Please refer to the AM335x Datasheet for the latest OPP values.

Voltage Rails

The following tables compare the power supplies for AM37x and AM335x:

AM37x Voltage Rails

SIGNAL	DESCRIPTION	VALUE
vdd_mpu_iva	MPU	0.97V - 1.33V *
vdd_core	Core	0.97V - 1.33V *
vdds	1.8-V I/O	1.8V
vdds_mem	Memory buffers	1.8V
vdds_mmc1	MMC1 dual voltage I/Os	1.8V / 3.0V
vdds_x	x dual voltage I/Os	1.8V / 3.0V
vdda_wkup_bg_bb	Wake-up LDO	1.8V
vdda_dac	Video DAC	1.8V
vdds_sram	SRAM LDOs	1.8V
vdda_dplls_dll	MPU, core DPLLs and DLL	1.8V
vdda_dpll_per	DPLLs (peripherals)	1.8V
vssa_dac	Ground for video buffers and DAC	0V
vss	Main ground	0V

* Note: Please refer to the AM37x Datasheet for the latest values.

AM335x Voltage Rails

SIGNAL	DESCRIPTION	VALUE
VDD_CORE	Core domain	1.1V
VDD_MPU *	MPU domain	0.95V - 1.26V
CAP_VDD_RTC	RTC domain input/LDO output	1.1V
VDDS_RTC	RTC domain	1.8V
VDDS_DDR	DDR IO domain (DDR2 / DDR3)	1.8V / 1.5V
VDDS	Dual voltage IO domains	1.8V
VDDS_SRAM_CORE_BG	Core SRAM LDOs, Analog	1.8V
VDDS_SRAM_MPU_BB	MPU SRAM LDOs, Analog	1.8V
VDDS_PLL_DDR	DPLL DDR, Analog	1.8V
VDDS_PLL_CORE_LCD	DPLL Core and LCD, Analog	1.8V
VDDS_PLL_MPU	DPLL MPU, Analog	1.8V
VDDS_OSC	System oscillator IOs, Analog	1.8V
VDDA1P8V_USB0	USB PHY, Analog, 1.8V	1.8V
VDDA1P8V_USB1	USB PHY, Analog, 1.8V	1.8V
VDDA3P3V_USB0	USB PHY, Analog, 3.3V	3.3V
VDDA3P3V_USB1	USB PHY, Analog, 3.3V	3.3V
VDDA_ADC	ADC, Analog	1.8V
VDDSHV1	Dual Voltage IO domain (1.8-V operation)	1.8V
VDDSHV2 *	Dual Voltage IO domain (1.8-V operation)	1.8V
VDDSHV3 *	Dual Voltage IO domain (1.8-V operation)	1.8V
VDDSHV4	Dual Voltage IO domain (1.8-V operation)	1.8V
VDDSHV5	Dual Voltage IO domain (1.8-V operation)	1.8V
VDDSHV6	Dual Voltage IO domain (1.8-V operation)	1.8V
VDDSHV1	Dual Voltage IO domain (3.3-V operation)	3.3V
VDDSHV2 *	Dual Voltage IO domain (3.3-V operation)	3.3V
VDDSHV3 *	Dual Voltage IO domain (3.3-V operation)	3.3V
VDDSHV4	Dual Voltage IO domain (3.3-V operation)	3.3V
VDDSHV5	Dual Voltage IO domain (3.3-V operation)	3.3V
VDDSHV6	Dual Voltage IO domain (3.3-V operation)	3.3V
DDR_VREF	DDR SSTL/HSTL reference input (DDR2/DDR3)	0.50*VDDS_DDR
USB0_VBUS	USB VBUS comparator input
USB1_VBUS	USB VBUS comparator input
USB0_ID	USB ID input	1.8V
USB1_ID	USB ID input	1.8V

* Note: These voltage rails are not available in the 13x13 package.

Clocks and PLLs

Input Clocks

AM37x Input Clocks

SIGNAL	DESCRIPTION	VALUE
sys_xtalin/out	High Frequency Input Clock	12, 13, 16.8, 19.2, 26, 38.4 MHz
sys_altclk	Alternative Input Clock	48 MHz or 54 MHz
sys_32K	Low Frequency Input Clock	32 KHz

AM335x Input Clocks

CLOCK NAME	SOURCE	VALUE
CLK_M_OSC	Master Oscillator	19.2, 24, 25, 26 MHz
CLK_32KHZ	Divide down of PER PLL output (PLL uses Master Osc)	32768 Hz Precise
CLK_RC_32KHZ	Internal RC Oscillator	16 - 60 kHz
CLK_32K_RTC	External 32768 Hz crystal with internal 32K Osc or external 32768 Hz clock	32768 Hz Precise

On AM37x, the high frequency clock, alternative input clock, and 32KHz clock were required to be sourced externally. The AM335x has the option to obtain the 32KHz clock from the high frequency 20MHz clock using an internal RTCDIVDER. If this is used, an external 32KHz clock source is not necessary. The 32KHz provides a clock for the following modules:

• RTC
• GPIO0/1/2/3
• TIMER1/2/3/4/5/6/7
• ARM
• SYNCTIMER

PLLs

AM37x has the following PLLs, all driven by the HF clock:

• DPLL1 - MPU
• DPLL3 - Core
• DPLL4 - Peripherals
• DPLL5 - Peripherals 2

AM335x has the following PLLs, driven by a crystal (CLK_M_OSC):

• Core PLL - for SGX, EMAC, L3S, L3F, L4F, L4_PER, L4_WKUP, PRUSS IEP, Debugss
• Peripheral (Per) PLL - for USB PHY, PRUSS UART, MMC/SD, SPI, I2C, UART
• MPU PLL - for MPU Subsystem (includes Cortex A-8)
• Display PLL - for LCD Pixel Clock
• DDR PLL - for EMIF

Power Management Feature Comparison

HW Provisions for Power Optimization/ Control	AM37x	AM335x
Operating Voltage-Frequencies (OPPs)	OPP50, OPP100, OPP130, OPP1G	OPP50, OPP100, OPP120, SRTurbo
Adaptive Voltage Scaling	Class 3 Smart Reflex, VDD1_MPU and VDD2_CORE	Class 2B Smart Reflex, VDD_CORE & VDD_MPU can be scaled. VDD_RTC is Fixed.
SRAM memory retention	Supported	All memories
Logic State Retention	Yes	No
Individually Switchable Power Domains	No support for individually ON/OFF of Power Domains	Full support for individually ON/OFF of Power Domains. Note, in RTC_Only mode even WAKEUP Domain can be OFF
Dynamically gating OFF of Clocks to one/more of groups of modules (clock domains) when inactive to conserve power	Yes	Yes
HW Auto Clock/Power Domain Dependency Management	Supported	Not Supported
Low Power Deep-Sleep State w/ Auto Wakeup	Not Supported	GPIO0 bank, UART0, RTC, I2C0, DMTimer 1ms, USB Resume and TSC/ ADC Control events
RTC Only Cold State	Not Applicable	Supported. System includes 32KHz Osc integrated with alarm/wake signaling interface w/ PMIC.
Splitting Of Primary Voltage Supply Rails	VDD_CORE, VDD_MPU	VDD_CORE, VDD_MPU*, VDD_RTC

* On 13x13 mm package option, VDD_CORE and VDD_MPU are merged.

Bootmodes

The available bootmodes for AM37x and AM335x are shown in the table below.

Available Bootmodes on AM37x and AM335x

AM37x	AM335x	Feature	Description
Y	Y	NOR	This mode allows booting from XIP booting devices, such as NOR flash memories. For AM37x, NOR Flash (up to 2 Gb, or 256M bytes) should be connected to the GPMC peripheral on GPMC_nCS0. GPMC_nCS0 is mapped to address 0x0800_0000. A data bus width of x16 is supported. The GPMC is clocked at 48MHz. For AM355x, NOR Flash (up to 1 Gb, or 128M bytes) should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 50MHz.
Y	Y	NAND	This mode starts downloading code from an NAND memory. For AM37x, NAND flash (from 512Mbit, or 64Mbyte) from should be connected to the GPMC peripheral on GPMC_nCS0. GPMC_nCS0 is mapped to address 0x0800_0000. A data bus width of x8 or x16 is supported. The GPMC is clocked at 48MHz. For AM335x, NAND flash (from 512Mbit, or 64Mbytes)should be connected to the GPMC peripheral on GPMC_CSn0. GPMC_CSn0 is mapped to address 0x8000_0000. A data bus width of x16 is supported. The GPMC is clocked at 50MHz.
N	Y	SPI	This mode starts downloading code from an SPI EEPROM or SPI Flash. For AM335x, the external SPI device should be connected to the SPI0 chip select 0 signal (SPI0_CS0). SPI EEPROM devices must use 24-bit addressing, and its read command must equal 0x03.
Y	Y	UART	In this mode, the UART sends a BOOTME request to the UART peripheral and waits for a response along with code from a host processor. Both AM37x and AM335x must be booted using a baud rate of 115200. AM37x can only boot from UART3. AM335x can only boot from UART0.
Y	Y	MMCSD	This mode starts booting code from an MMC/SD Controller. For AM37x, the MMC/SD cards should connected to either MMC1 or MMC2. 1.8V or 3.3V I/O voltage is supported on MMC1, and only 1.8V I/O voltage is supported on MMCC2. (External transceiver mode on MMC2 is not supported.) The supported clock frequencies are up to 400 kHz (identification mode) and 20 MHz (data transfer mode). For AM335x, the MMC/SD cards should connected to either MMC0 or MMC1. 1.8V or 3.3V I/O voltage is supported on MMC0, and only 1.8V I/O voltage is supported on MMC1. The supported clock frequencies are up to 400 kHz (identification mode) and 10 MHz (data transfer mode).
N	Y	EMAC	This mode starts booting code from the EMAC port. For AM335x, EMAC boot uses the CPGMAC port 1 of the device.
Y	N	DiskOnChip	In this mode, the DiskOnChip is connected just like a regular NOR device.
Y	N	HS USB	In this mode, the ROM code boots from a USB interface.

Multimedia Hardware Components

Display

AM37x has a display subsystem (DSS) that supports the following resolutions: XGA, WXGA, SXGA+, and HD 720p.

AM335x has a simple LCD controller with no preprocessing operations such as preview, overlay, blending, resizing, etc. The AM335x LCD controller supports up to WXGA resolution.

Camera SubSystem

A camera subsystem is not supported on AM335x.

Communication Interfaces

MMC/SD

The AM37x and AM335x devices support different versions of industry standards (shown below).

Feature Comparison

FEATURE	AM37x	AM335x
Spec Compliance	MMC v4.2 * SDIO v2.0 SD card v2.0	MMC v4.3 SDIO v2.0 SD card v2.0
Data width **	8-bit (MMC2/3) 4-bit (MMC1)	8-bit (MMC0/1/2)
Max Clock Rate	48MHz (MCC), 48MHz (SD), 48MHz (SD)	48MHz (MCC), 48MHz (SD), 48MHz (SD)

* Note full compliance with the MMC command/response sets and MMC bus testing procedure, as defined in the Multimedia Card System Specification, v4.2, does not prevent the use of e.MMC version 4.3 (or 4.4) devices with the AM37x, because e.MMC devices are backward compatible.

** Note the supported data width is subject to pinmux constraints.

USB

The main differences between the two devices with respect to USB is the integrated PHYs and the more flexible operation in the AM335x.

The AM37x requires an external PHY with both the USB-OTG and USB1-3 host ports. Also, the USB1-3 ports are only capable of host mode operation, at either high speed or full speed mode (not both).

The AM335x has 2 USB ports capable of host and OTG operations. Both ports have an integrated PHY.

I2C

The I2C ports are binary compatible same between the two devices.

AM37x supports 3 general I2C ports. The I2C ports can support up to 3.4Mbps high speed transmissions, along with the usual 100/400Kbps operation.

AM335x supports 3 general I2C ports. The ports only support 100/400Kbps operation. No high speed mode is supported.

UART

The UART modules on both devices are functionality compatible with the TL16C750 (and TL16C550) UART. The primary differences between devices are the number of UARTs and supported capabilities.

AM37x has 4 UARTs. Only UART3 has IrDA capabilities. UART 4 does not support flow control.

AM335x has 6 UARTs, all of which support IrDA, CIR, and flow control. Full modem control is only available on 1 UART instance. AM335x allows 1 instance of UART rx/ tx lines to be muxed with USB DP/ DM lines.

MCBSP/McASP

AM37x has 5 McBSP ports and no McASP ports

AM335x has no McBSP ports and 2 McASP ports.

The McASP is a superset of the McBSP. It is suggested to use the McASP ports for McBSP functionality. Note the McASP ports on AM335x have less buffers for internal FIFO and audio loopback and no sidetone support.

HDQ-1Wire

The module does not exist on AM335x. It is suggested to use either I2C or GPIO for this type of functionality (eg, battery monitor).

Timers

GPTimer

The GPTimers on both devices are binary compatible.

AM37x has 11 32-bit GPTimers. Three GPTimers (GPTIMER1, GPTIMER2, and GPTIMER10) support 1-ms tick with 32,768 Hz functional clock generated. Only 4 GPTimers (GPT_8 - GPT_11) are pinned out.

AM335x supports seven (7) 32-bit GPTimers. One GPTimer (DMTIMER1) is specialized for accurate 1mS OS Ticks. Only 4 GPTimers (DMTIMER4 - DMTIMER7) are pinned out.

WDTimer

AM37x has 2 32-bit Watchdog Timers. AM335x has 1 32-bit Watchdog Timer.

32-kHz Sync Timer

The 32-kHz sync timer does not exist on AM335x.

Misc

GPIOs

The GPIO modules between the two devices are binary compatible. The only difference is in the number of banks and I/O capabilities.

AM37x supports 6 banks of GPIO signals. Each bank supports 32 GPIOs and two interrupts. All GPIOs are 1.8V I/Os, with the exception of those muxed with MMC1 which are 3.0V capable.

AM335x supports 4 banks of GPIO signals. Each bank supports 32 GPIOs and two interrupts. All GPIOs are 1.8V/3.3V capable, depending on which I/O group the pin falls in. Most LVCMOS IO`s on AM335x are configurable as GPIO.

New interfaces in AM335x

The following are new interfaces in the AM335x device that do not exist in AM37x. Any details about these interfaces can be found in the Technical Reference Manual for AM335x.

• CAN - Controller Area Network Interface
• eCAP
• Ethernet
• eQEP
• PRUSS - Programmable Real-time Unit SubSystem
• PWM
• RTC
• TS/ADC

Pin and package

The AM37x and the AM335x devices are offered different mechanical packages. The physical dimensions and pin out of the packages are also different. The table below lists the variations between the AM37x and the AM335x devices.

Pin and Package Comparison

Device	Size (mm)	Pitch (mm)	No. of Pins	POP	Package Designator
AM37x	12 x 12 mm	0.5 mm top, 0.4 mm bottom	515	Supported	s-PBGA (CBP Suffix)
	14 x 14 mm	0.65 mm top, 0.5 mm bottom	515	Supported	s-PBGA (CBC Suffix)
	16 x 16 mm	0.65 mm	423	Not supported	s-PBGA (CUS Suffix)
AM335x	13 x 13 mm	0.65 mm	298	Not supported	s-PBGA (ZCE Suffix)
	15 x 15 mm	0.80 mm, with VCA	324	Not supported	s-PBGA (ZCZ Suffix)