AM335x StarterWare Power management

Power Management

         The power-management framework is built with three levels of resource management: clock, power, and voltage management.These management levels are enforced by defining the managed entities or building blocks of the power-management architecture, called the clock, power, and voltage domains. A domain is a group of modules or subsections of the device that share a common entity (for example, common clock source, common voltage source, or common power switch). The group forming the domain is managed by a policy manager. For example, a clock for a clock domain is managed by a dedicated clock manager within the power, reset, and clock management (PRCM) module. The clock manager considers the joint clocking constraints of all the modules belonging to that clock domain. For more details please refer AM335x TRM.

         Power Management is handled by softwares running on A8 and CM3. This page explains about the software running on A8. CM3 software and prebuild binary can be downloaded from here. The communication between A8 and CM3 is through IPC registers. The communication protocol is explained below.

Features supported

Features	EVM	EVM-SK	Beaglebone
Deep Sleep 0	Supported	Supported	Supported
Deep Sleep 1	Supported	Supported	Supported
RTC only *	Supported **	Not Supported	Not Supported
Standby	Supported	Supported	Supported
DVFS(MPU)	Supported	Supported	Not Supported
Smart Reflex	Not Supported	Not Supported	Not Supported
Dynamic power switching	Realized via deep sleep modes	Realized via deep sleep modes	Realized via deep sleep modes
Static Leakage Management	Realized via deep sleep modes	Realized via deep sleep modes	Realized via deep sleep modes

(*)  - Supported from SoC version 2.0

(**) - Supported from EVM Rev. 1.5x

Sleep modes

1. DS0 - Refer TRM section 8.1.4.3.4
   
2. DS1 - Refer TRM section 8.1.4.3.3
   
3. Standby - Refer TRM section 8.1.4.3.2
   
4. RTC Only - Refer TRM section 8.1.4.3.5
   

Programming Sequence

      The sequence of steps to be followed to enter low power mode are listed below. The following state diagram depicts the same.

       

Initialization sequence

        The following steps are to be followed to enable the device to enter low power mode.

1. Initialize the interrupt controller and configure it to receive TXEV event from CM3
   
2. Load CM3 image (which is embedded (as header file) as part of A8 binary), to CM3 address space (0x44D00000u).
   
3. Release CM3 from reset and wait for ack (TXEV)
4. Initailize all the peripehrals used in the application (including mailbox)
5. Enter steady state execution and wait for command to enter deep sleep state.

Entering Deep sleep

      The sequence listed below is applicable for Deep Sleep0 (a subset of these are applicable for Deep Sleep1). Once the command for entering Deep sleep mode is received the following steps are to be followed.

Configure the Deep sleep command

            Configure the DS command ID and the relevant parameters in IPC registers. The format of the same is given below.

           

Command IDs

      Following are the command IDs supported,

CMD_ID	Value	Description
CMD_DS0	0x3	1. Initiates force_sleep on interconnect clocks 2. Turns off the MPU and PER power domains 3. Configures the system for disabling MOSC when CM3 executes WFI
CMD_DS1	0x5	1. Initiates force_sleep on interconnect clocks 2. Turns off the MPU power domains 3. Configures the system for disabling MOSC when CM3 executes WFI
CMD_STANDBY	0xb	1. MOSC remains ON 2. Turn off the MPU power domain
CMD_RESET_STATE_MACHINE	0xe	1. Reset CM3 state machine

Command status

      The possible status values are listed below.

CMD_STAT	Value	Description
PASS	0x0	1. In init phase this denotes that CM3 was initialized successfully. 2. When other commands are to be executed, this indicates completion of command.
FAIL	0x1	. In init phase this denotes that CM3 could not initialize properly. 2. When other commands are to be executed, this indicates some error in carrying out the task.
WAIT4OK	0x2	CM3 INTC will catch the next WFI of A8 and continue with the pre-defined sequence
IN_PROGRESS	0x3	Early indication of command being carried out

Command Parameters

      The following structure shows the different parameters to be configured by A8. Only a subset of parameters are valid for a given command.

typedef struct
{
    /* Address to where the control should jump on wake up on A8 */
    unsigned int resumeAddr:32;

    /* MOSC to be kept on (1) or off (0) */
    unsigned int moscState :1;

    /* Count of how many OSC clocks needs to be seen before exiting deep sleep mode. Default = 0x6A75 */
    unsigned int deepSleepCount :16;

    /* If vdd_mpu is to be lowered, vdd_mpu in 0.01mV steps */
    unsigned int vddMpuVal :15;

    /* Powerstate of PD_MPU */
    unsigned int pdMpuState :2;

    /* State of Sabertooth RAM memory when power domain is in retention */
    unsigned int pdMpuRamRetState :1;

    /* State of L1 memory when power domain is in retention */
    unsigned int pdMpul1RetState :1;

    /* State of L2 memory when power domain is in retention */
    unsigned int pdMpul2RetState :1;

    /* State of Sabertooth RAM memory when power domain is ON */
    unsigned int pdMpuRamOnState :2;

    /* Powerstate of PD_PER */
    unsigned int pdPerState :2;

    /* State of ICSS memory when power domain is in retention */
    unsigned int pdPerIcssMemRetState :1;

    /* State of other memories when power domain is in retention */
    unsigned int pdPerMemRetState :1;

    /* State of OCMC memory when power domain is in retention */
    unsigned int pdPerOcmcRetState :1;

    /* State of ICSS memory when power domain is ON */
    unsigned int pdPerIcssMemOnState :2;

    /* State of other memories when power domain is ON */
    unsigned int pdPerMemOnState :2;

    /* State of OCMC memory when power domain is ON */
    unsigned int pdPerOcmcOnState :2;

    /* Wake sources */
    /* USB, I2C0, RTC_ALARM, TIMER1, UART0, GPIO0_WAKE0, GPIO0_WAKE1, WDT1, ADC_TSC */
    unsigned int wakeSources :13;

    unsigned int reserved :1;

    /* Command id to uniquely identify the intented deep sleep state */
    unsigned int cmdID:16;

    /* Delay for RTC alarm timeout. Default = 2secs */
    unsigned char rtcTimeoutVal :4;

}pmAttributes;

Save Peripheral and IO Pad Context

             On power down of peripheral domain the context of the pripheral modules is lost. To retain the context on resume from sleep mode, the context of the necessary modules under peripheral domain has to be saved in DDR. On resume the saved context has to restored from DDR.

Note: Save Peripheral and IO Pad Context of all active peripherals in system for Deep Sleep0 only.
      For other sleep modes it is recommended to Save Peripheral and IO Pad Context of the peripheral reconfigured for wakeup. 

Halt Peripherals

             Disable or Halt any active transactions and configure system interfaces or modules to idle state.

Wake CM3

             Currently CM3 will be in sleep state executing WFI instruction. An interrupt will cause it to wake from wfi. Here the mailbox interrupt is generated to wake CM3 from WFI. A8 waits for sync (txev) from CM3.

Clear Mailbox

             After getting the sync from CM3, the MPU (A8) clears the mailbox, by reading the message and clearing the new message status. Since in SA, CM3 is not capable of clearing the mailbox, A8 clears it.

Configure wakeup sources

            Configure the designated wakeup peripheral. Configuration of wakeup source depends on the sleep mode.

For sleep modes other than standby only sources under wakeup domain can be configured as wake source. Configure the peripheral in smart-idle-wakeup mode and disable the wakeup peripheral (Timer is an exception, timer module should not be disabled it timer is expected to wakeup the device). Possible wakeup sources are,

• GPIO0 bank
  
• dmtimer1_1ms (timer based wakeup)
• USB2PHY (USB resume signaling from suspend) – Both USB ports supported.
• TSC (touch screen controller, ADC monitor functions )
• UART0 (Infra-red support)
• RTC (RTC Alaram)
• I2C0
  

Any source can be configured for resume from standby. Any peripheral interrupt can cause resume from standby. Configure the wake source for interrupt and donot disable the peripheral.

Note: Not all sources are demonstrated in StarterWare.

Disable modules

          EMIF shall not be disabled at this stage. Only modules not configured for wakeup shall be disabled for standby mode. For other sleep modes all modules have to be disabled.

Reduce peripherals frequency

          Since the VDD_MPU voltage will be reduced (to OPP 50 value) before entering Deep sleep, the operating frequency of MPU and peripherals have to be reduced to OPP 50 vlaues.

Reduce VDD voltages

          The VDD_MPU voltage is reduced to 0.95v to reduce leakage during deep sleep state.

Disable Interrupts

          Diasble IRQ interrupts. This will ensure that DDR is not accessed when trying to execute the ISR.

Save MPU context

         Save MPU context in OCMC ram, which will be retained during deep sleep mode.

Save EMIF context

         Ensure that before disabling the EMIF module its context is saved.

Note: Save EMIF Context is required for Deep Sleep0 and Standby Mode. 

DDR Self-Refresh

         Put DDR into self-refresh mode to retain the DDR contents in sleep mode.

Disable EMIF Clock

         For further optimisation of power disable EMIF module. Ensure that EMIF context is saved before disabling module.

Note: EMIF has to be disabled for Deep Sleep0 and Standby Mode. 

Configure DDR for low power

1. Configure DDR I/O for weak pull down.
2. Configure DDR to Dynamic Power Down.
   
3. Disable VTP.
   
4. Enable SRAM LDO Ret Mode.
   

Bypass PLLs

         Configure PLLs to Bypass mode.

WFI

           When A8 (A8 module configured to disable) executes wfi, CM3 gets an interrupt and starts deep sleep entering process. CM3 disables all the power domain, configures the memory retention and Master OSC (disable or not) based on the parameters passed by A8 along with the deep sleep command.

Note: When A8 is connected to debugger and executes wfi, CM3 will not receive interupt.
       Only when debugger is not connected CM3 will receive the interrupt.

Wakeup from Deep Sleep

           The following steps are to be followed before executing the steady state functionalities.

Re-Lock PLLs

          On wakeup relock the PLLs.

Revert low power configurations for DDR

1. Enable SRAM LDO Ret Mode.
   
2. Enable VTP.
   
3. Revert DDR Dynamic Power Down.
   
4. Disable weak pull down for DDR I/O.

Enable EMIF Clock

          Enable EMIF Modules before restoring the EMIF context.

Note: EMIF has to be enabled for Deep Sleep0 and Standby Mode.

Restore EMIF Context

          Restore the EMIF context saved before entring sleep.

Note: Restore EMIF Context is required for Deep Sleep0 and Standby Mode.

Exit DDR from self-refresh mode

          Configure DDR to exit from self-refersh.

Restore MPU context

          Restore MPU context from OCMC ram, which are retained during deep sleep mode.

Configure Vector table

          Configure the vector table base address in CP15 register.

Enable Interrupts

          Enable IRQ interrupts. The system is now capable of handling interrupts.

Enable all the mdoules

          Enable all the modules (except EMIF) and configure PLLs to the required configuration.

Disable Wakeup

          Disable the wakeup source, so that the normal interrupt is not registered with CM3 as wakeup interrupt. If the wake source is not disabled, this might cause the device to wake up immediately after entering the Deep sleep (in the next cycle).

Restore VDD voltages

          The VDD_MPU is voltage is restored to the value before sleep.

Reinitalize the peripherals

          The peripherals in PD_PER power domain need to be reinitialized, since PD_PER is switched off during deep sleep.

Note: Restore peripheral context and I/O pad configuration of active peripherals in system for Deep Sleep0.
      For other sleep modes it is recommended to Restore Peripheral and IO Pad Context of the peripheral reconfigured for wakeup. 

Now the system is ready for next cycle of sleep/wake sequence.

Code flow for suspend/resume or sleep/wakeup sequence - on (A8) MPU side

     Note: A8 comunicates with CM3 for Wake CM3 & Configure Sleep Mode, WFI and Reset CM3.
                Wake CM3 & Configure Sleep Mode - to configure Sleep Mode
                WFI - to enter sleep mode
                Reset CM3 - to clear the Sleep Mode configuration 

RTC Only mode

Refer TRM section 8.1.4.3.5 for RTC Only mode.
To execute RTC Only mode

• Configure RTC module clock to external CLK_32K_RTC clock.
• RTC alarm2 is configured to put the system in RTC Only mode.
• RTC alarm and/or external wake pin are configured to wakeup system from RTC Only.
• Refer TRM section 20.3.5.34 to enable RTC Only wake.

Known Issue

• In RTC Only mode distorted image is observed on LCD with EVM 1.5x.
• On EVM 1.5x, there is stray voltage observed on VDDSHV1/3/5/6 supplies due to a board hardware issue.

Executing Example Applications

In StarterWare package the power management examples are integrated with OOB. The "PM" slide in OOB demonstrate enter/exit of different sleep modes. Steps to execute the sample application and the expected behaviour are given below.

1. Load the OOB application on to target.
   
2. If the image(.out) is loaded through debugger, the debugger has to be disconnected after executing (run) the image. Otherwise the device will not be able to enter sleep state. Alternatively the user can load the binary file form MMC/SD or SPI or NAND.
   
3. Navigate to the "PM" slide and trigger the sleep mode (in the examples supplied the trigger sources supported is touch screen)
   
4. Now the device will be in sleep state consuming low power. The power consumption across different rails (on EVM) can be calculated by measuring the drop across sense resisters in different rails. Refer power consumption for more details.
   
5. To wake the device from sleep state, trigger the wake source. Listed below are supported wake sources for EVM, EVM-SK & Beaglebone
   

Wake Source	EVM	EVM-SK	Beaglebone	Remarks
Touch Screen	Supported	Supported	Not Supported
Timer1	Supported	Supported	Supported	Not supported for Standby
Uart0	Supported	Supported	Supported	For standby external peripheral to be configured for GPIO wake
GPIO0	Supported (SW9)	Supported (SW3)	Not Supported
RTC Alarm	Supported	Not Supported	Not Supported	Supported from SoC Version 2.0 and Standby
Timer6	Supported	Supported	Supported	Wakeup with modules in peripheral domain supported for Standby only
Ext Wake Pin	Supported (SW7)	Not Supported	Not Supported	Supported for RTC Only mode

Note

• Wake source selection is not applicable for RTC only

Now the device will be in normal state. This cycle can be repeated.

Converting CM3 binary to header file

The following steps are to be followed to convert CM3 binary to header file.

1. The source for binToc is located at StarterWare\\tools\binToC.
   
2. Compile the above to get the converter executable
3. conversion command: a.exe <CM3_binary.bin>  <CM3_image.h>
4. Use the generated header in your application

Power Consumption

This section indicates the power measured for all power rails when system is in DeepSleep0, DeepSleep1 and Standby. The measurements are done using EVM 1.5x with OOB application from latest StarterWare Software version.

Power Rail	Deep Sleep0 (milliwatts)	Deep Sleep1 (milliwatts)	Standby (milliwatts)
VDD_CORE*	1.96	6.10	16.31
VDD_MPU	0.22	0.22	0.22
VDDS_RTC	0.04	0.04	0.04
VDDS_DDR	0.05	0.05	0.05
VDDS	0.86**	0.35	0.35
VDDS_SRAM_CORE_BG	0.17	0.17	1.94
VDDS_SRAM_MPU_BB	0.01	0.01	0.01
VDDS_PLL_DDR	0.00	0.00	0.00
VDDS_PLL_CORE_LCD	0.00	0.00	0.00
VDDS_PLL_MPU	0.00	0.00	0.00
VDDS_OSC	0.00	0.00	1.23
VDDA_1P8V_USB0_1	0.00	0.00	0.00
VDDS_A3P3V_USB0_1	0.07	0.07	0.07
VDDA_ADC	0.00	0.00	0.00
VDDSHV1	0.07	0.47	0.47
VDDSHV2	0.07	0.07	0.08
VDDSHV3	0.08	0.11	0.10
VDDSHV4	0.04	0.09	0.10
VDDSHV5	0.06	0.18	0.18
VDDSHV6	0.38	0.69	0.65
Total Power (Sum of all Rails)	4.08	8.63	21.93

Note

• With the following modifications power can be further reduced
  • (*) - Configuring VDD_CORE to 0.95V. This configuration has to be done in CM3. It is not implemented in current release.
  • (**) - Configuring CONTROL_CONF_ECAP0_IN_PWM0_OUT iopad as GPIO with pull up/down disabled. With this modification distortion is observed on LCD in sleep state.