AM335x GPMC to OMAP-L13x HPI Interface

Introduction

There are many types of embedded systems that require the combination of the AM335x applications processor with the OMAP-L13x DSP+ARM processor. In such systems it is often necessary to establish an inter-processor communication link for data and control message exchange between the two devices. The AM335x general purpose memory controller (GPMC) can be used with the OMAP-L13x host port interface (HPI) to establish a link suitable for inter-processor communication.

The OMAP-L13x HPI is a parallel bus that enables an external host processor, such as the AM335x, to access the memory addresses of the OMAP-L13x. The bus interface logic of the HPI is similar to that of an asynchronous NOR Flash memory making it compatible with the external memory interface of most host processors ; in this case the GPMC of AM335x. The OMAP-L13x HPI is often referred to as a “slave” interface, since it is not able to initiate transfers without an external host processor. Similarly, the AM335x can be referred to as the “master” of the interface since it initiates all transfers through its GPMC bus.

This document provides a summary of the significant information about AM335x GPMC to OMAP-L13x HPI interface and its timing analysis. This interface guide will be helpful to the users to understand the GPMC to HPI interface and its timing constraints.

The details about the GPMC and HPI interfaces are provided in the following links.

• AM335x GPMC
• OMAP-L1x HPI

GPMC to HPI Interface

GPMC to HPI Connectivity Diagram

The figure below shows the connectivity details between AM335x GPMC and OMAP-L1x HPI.

GPMC to HPI Interface Block Diagram

HPI Timing & Switching Characteristics

The below table provides the HPI timing requirements and its switching characteristics.

HPI Timing & Switching Characteristics

No.	Voltage Rating	1.3V, 1.2V		1.1V		1.0V		Unit	Cycle	Type
	Parameter	Min	Max	Min	Max	Min	Max
1	tsu(SELV-HSTBL)	5		5		5		ns	R	Timing Requirement
3	tw(HSTBL)	15		15		15		ns	R/W	Timing Requirement
4	tw(HSTBH)	2M (11)		2M (11)		2M (11)		ns	R/W	Timing Requirement
5	td(HSTBL-HRDYV)		15		17		22	ns	R/W	Switching Characteristics
6	ten(HSTBL-HDLZ)	1.5		1.5		1.5		ns	R	Switching Characteristics
7	td(HRDYL-HDV)		0		0		0	ns	R	Switching Characteristics
8	toh(HSTBH-HDV)	1.5		1.5		1.5		ns	R/W	Switching Characteristics
11	tsu(HDV-HSTBH)	5		5		5		ns	W	Timing Requirement
12	th(HSTBH-HDV)	2		2		2		ns	W	Timing Requirement
13	th(HRDYL-HSTBH)	2		2		2		ns	R/W	Timing Requirement
14	tdis(HSTBH-HDHZ)		15		17		22	ns	R	Switching Characteristics
15	td(HSTBL-HDV)		15		17		22	ns	R	Switching Characteristics
18	td(HSTBH-HRDYV)		15		17		22	ns	W	Switching Characteristics

GPMC WAIT Sampling and Bus Turnaround

The details about the GPMC WAIT and bus turnaround are available in section 7.1.3.3.8.3 External Signals in AM335x TRM.

• AM335x TRM

GPMC to HPI Read/Write Access

This section describes about the various timing parameters and timing diagrams of GPMC to HPI read and write accesses.

GPMC to HPI Read Timing Diagram

The figure below shows the timing details of GPMC to HPI Read access.

GPMC to HPI Read Timing Diagram

GPMC Read Timing Diagram

The figure below shows the timing details of GPMC Read access.

GPMC Read Timing Diagram

GPMC Read Timing Parameters

The below table provides the GPMC timing parameters for read access.

GPMC Timing Parameters for Asynchronous Read Access

GPMC Parameter Name	Formula	Duration (ns)	Number of Clock Cycles (F = 100 MHz)	GPMC Register Configurations	Notes
CLKActivationTime	N/A (asynchronous mode)
CSONTime	Start as early as possible	0	0	CSONTIME = 0
OEONTime	tsu(SELV-HSTBL)	5	1	OEONTIME = 1h	This provides 2 GPMC_CLK cycles min high pulse. HPI min. high pulse time for all back to back accesses is tw(HHSTBH) = 2M (11ns @ 375MHz)
AccessTime	OEONTime + td(HSTBL-HDV) + WAIT Sampling	45	5	ACCESSTIME = 5h	tsu(SELV-HSTBL) = 5ns. td(HSTBL-HDV) = 15ns, 17ns, or 22ns, depending on CVdd.
OEOFFTime	AccessTime + 1 cycle	55	6	OEOFFTIME = 6h	This provides some hold time from th(HSTBH-HDV).
CSReadOFFTime	OEOFFTime + 1 cycle	65	7	CSRDOFFTIME = 7h	Provides 1 cycle hold time for access to complete.
RDCycleTime	CSReadOFFTime	65	7	RDCYCLETIME = 7h	Could make = CSRDOFFTIME so that CS stays asserted for B2B. tdis(HSTBH-HDHZ) = 15ns, 17ns, 22ns, depending on CVdd.

Assumption and Conclusion for Read Access

• Analysis assumes 100MHz GPMC clock and OMAP-L1x CVdd = 1.1V or 1.2V.
• The OE off time must be > Access time so that OE de-assertion is properly delayed by WAIT pin monitoring.
• First and second half read timings are set identically because GPMC only provides one set of timings per CS.
• Minimum read cycle time is 2 x 70ns = 140ns.
• Peak read rate is (1/140ns)*4 bytes = 28.6MBytes/sec.

GPMC to HPI Write Timing Diagram

The figure below shows the timing details of GPMC to HPI Write access.

GPMC to HPI Write Timing Diagram

GPMC Write Timing Diagram

The figure below shows the timing details of GPMC Write access.

GPMC Write Timing Diagram

GPMC Write Timing Parameters

The below table provides the GPMC timing parameters for write access.

GPMC Timing Parameters for Asynchronous Write Access

GPMC Parameter Name	Formula	Duration (ns)	Number of Clock Cycles (F = 100 MHz)	GPMC Register Configurations	Notes
CLKActivationTime	N/A (asynchronous mode)
CSONTime	Start as early as possible	0	0	CSONTIME = 0
WEONTime	tsu(SELV-HSTBL)	5	1	WEONTIME = 1h	This provides 2 GPMC_CLK cycles min. high pulse. HPI min. high pulse time for all back to back accesses is tw(HHSTBH) = 2M (11ns @ 375MHz)
AccessTime	Applicable only to WAITMONITORING (the value is the same as for read access)	45	5	ACCESSTIME = 5h
WEOFFTime	AccessTime + 1 cycle	55	6	WEOFFTIME = 6h	This provides some hold time from th(HSTBH-HDV).
CSWriteOFFTime	WEOFFTime + 1 cycle	65	7	CSWROFFTIME = 7h	Provides 1 cycle hold time for access to complete.
WRCycleTime	CSWriteOFFTime	65	7	WRCYCLETIME = 7h	Could make = CSWROFFTIME so that CS stays asserted for B2B.
BusTurnAroundTime	At least 1 cycle	10	1	BUSTURNAROUNDTIME = 1h	This is required to prevent data bus contention from previous read, tdis(HSTBH-HDHZ) . tdis(HSTBH-HDHZ) = 15ns, 17ns, 22ns, depending on CVdd.

Assumption and Conclusion for Write Access

• Analysis assumes 100MHz GPMC clock and OMAP-L1x CVdd = 1.1V or 1.2V.
• The WE off time must be > Access time so that WE de-assertion is properly delayed by WAIT pin monitoring.
• First and second half write timings are set identically because /HRDY can de-assert (not ready) in either cycle.
• The BusTurnAround parameter must be used to insert at least one cycle between a read followed by a write.
• Minimum write cycle time is 2 x 70ns = 140ns.
• Peak write rate is (1/140ns)*4 bytes = 28.6MBytes/sec.